Scaling down was applied during the last decades to increase the performance of integrated devices. A further reduction of the geometrical dimensions, however, is limited especially below 100 nm by different physical, technological, and economic reasons. Therefore the research is focussed to the application of new materials resulting in an increase of the performance of future devices. Especially tetragonally strained silicon (or strained silicon) is intensively studied because of the carrier transport enhancement to improve current drive in Si MOSFETs. Further advantages are obtained by combination of strained silicon with SOI-specific benefits.
The realization of large diameter strained silicon on insulator (sSOI) substrates, their characterization and implementation into advanced device processes are objectives of the TESIN project. Partners within the project are industrial companies (AMD Saxony, Dresden, Infineon Technologies, Munich (since 2006 Quimonda AG, Dresden), Siltronic AG, Burghausen, IMEC, Leuven, Aixtron AG, Aachen) and research institutes (Research Centre, Juelich, Max Planck Institute of Microstructure Physics, Halle).
The TESIN project is funded by the German Federal Ministry of Education and Research