Micro-lasers and high-speed photodetectors by lateral III-V growth on patterned SOI using MOCVD

  • Datum: 26.09.2022
  • Uhrzeit: 11:00
  • Vortragende: Prof. Kei May Lau
  • Ort: Max-Planck-Institut für Mikrostrukturphysik, Weinberg 2, 06120 Halle (Saale)
  • Raum: Lecture Hall, B.1.11
Micro-lasers and high-speed photodetectors by lateral III-V growth on patterned SOI using MOCVD


To efficiently couple light between active and passive components for Si photonics, we developed the lateral aspect ratio trapping (LART) technology to grow lasers and high-speed photodetectors on patterned commercial SOI substrates for integrated Si photonics. Multimode and single-mode lasing from lateral quantum wells (QWs) as the gain media using LART have been achieved in the 1433 -1630 nm band with varying dimensions of micro-ring lasers. High-performance PDs were also constructed on the monolithic InP/SOI platform with laterally grown p-i-n structures and show open eye diagram exceeding 40 Gb/s.


Kei May Lau is a Research Professor in the Department of Electronic Engineering at the Chinese University of Hong Kong. She was a Chair Professor of Electronic and Computer Engineering at the Hong Kong University of Science & Technology (HKUST). She received her degrees from the University of Minnesota and Rice University and served as a faculty member at the University of Massachusetts/Amherst until 2000. Prof. Lau is a Fellow of the IEEE, Optica (formerly OSA), and the Hong Kong Academy of Engineering Sciences. She is also a recipient of the IET J J Thomson medal for Electronics, OSA Nick Holonyak Jr. Award, IEEE Photonics Society Aron Kressel Award, US National Science Foundation (NSF) Faculty Awards for Women (FAW) Scientists and Engineers, and Hong Kong Croucher Senior Research Fellowship. She was an Editor of the IEEE Transactions on Electron Devices (1996-2002) and Electron Device Letters (2016-2019), an Associate Editor for the Journal of Crystal Growth and Applied Physics Letters. Lau’s research work is focused on the development of monolithic integration of semiconductor devices on industry-standard silicon substrates.

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